Experience

Perceptia Devices – IC Design Intern

Apr 2024 – Present

Responsibilities & Skills

CMOS Integrated Circuit Design Flow

• Schematic design, simulation, layout, layout-vs-schematic (LVS) verification, and parasitic extraction using EDA tools in Cadence Virtuoso

Post-Silicon Verification and Characterisation of Test Chips

• Set up and debugged an FPGA-based hardware interface for testing and development.
• Wrote Python scripts to automate data extraction
• Processed test data and generated clear summaries to support analysis
• Presented key findings and performance metrics to design engineers

Notable Projects

On-Chip Adaptive Impedance Matching Circuit (In Progress)

• Designing an on-chip circuit in 22nm CMOS to adaptively tune the impedance of a transmit driver for optimal 50-ohm matching
• Undertaking this as part of undergraduate thesis with industry under academic supervision

Characterisation Software Audit

• Gained familiarity with Verilog, Clojure, and Python-based test infrastructure
• Produced comprehensive documentation outlining system functionality
• Wrote code to fix multi-threading issues and improve support for SCPI instrument communication
• Improved error handling robustness and code readability

Technical Support for Broken PCB

• Diagnosed a customer-returned, damaged PCB by reviewing the KiCad design and using a multimeter to probe test points and identify shorts